Semiconductor device and communication interface circuit

ABSTRACT

A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Application No. 2012-011639 filed onJan. 24, 2012 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and acommunication interface circuits. The present invention can be suitablyutilized for a semiconductor device that short-circuits terminals and acommunication interface circuit including this semiconductor device, forexample.

Recently, USB (Universal Serial Bus) Specifications have been widelyspread as a measure for realizing data communication between electronicdevices and/or information processors. Above all, a computer, aperipheral device, and the like compliant with USB 2.0 among USBSpecifications are widely used.

Here, also in the initial USB 2.0 Specification, by coupling a host(e.g., a computer) and a device (e.g., a portable music player) providedwith a battery to each other, the charging of the battery of the devicewas possible. However, the upper limit of a supply power in this case islimited to 5 V/500 mA, and thus there is a strong demand for increasingthe upper limit. This is because when the power supply capability on thehost side increases, the battery charging on the device side is alsoquickly completed.

Therefore, an additional specification has been formulated with respectto USB 2.0 Specification. Non-patent document 1 (USB Implementers Forum,Inc, “Battery Charging Specification Revision 1.2”, Dec. 7, 2010,[online], and the Internet<URL:http://www.usb.org/developers/devclass_docs>, searched on Jan. 17,2012) discloses an additional specification (Revision 1.2) with respectto USB 2.0 Specification. Moreover, Patent Document 1 (Japanese Patent.Laid-Open No. 2011-217513) discloses a battery charger for electronicdevices compliant with USB Charging Specification (Revision 1.1) beforebeing revised to 1.2.

SUMMARY

Note that, each disclosure of the above-described conventional arts ishereby incorporated by reference in its entirety. The following analysishas been made by the present inventors.

As described above, the additional specification has been formulatedwith respect to USB 2.0 Specification. In this specification, theadditional specification disclosed in Non-patent document 1 is denotedas USB Battery Charging Specification 1.2 and will be described below.In USB Battery Charging Specification 1.2, a port defined as a CDP(Charging Downstream Port) and a port defined as a DCP (DedicatedCharging Port) are added.

In USB Battery Charging Specification 1.2, in order to allow fordiscrimination between these ports, differential signal lines D+ and D−need to be opened or short-circuited in accordance with the type of theport. More specifically, when a host operates as a CDP, the differentialsignal lines D+ and D− are opened (the both signal lines are notshort-circuited). Moreover, when operating as a host DCP, thedifferential signal lines D+ and D− are short-circuited. In USB BatteryCharging Specification 1.2, these specifications are specified.

Therefore, the present inventors have examined a circuit configurationfor implementing the specification, and have conceived arranging atransfer gate between the differential signal lines D+ and D−. Incontrast, a host, in confirming the mounting of a device, determineswhether or not the potential of the differential signal line D+ (ordifferential signal line D−) has exceeded a threshold value. Forexample, when the potential of the differential signal line D+ is equalto or greater than a predetermined threshold value and also when thepotential of the differential signal line D− is equal to the groundvoltage, a host determines that the device has been mounted. In thiscase, there may be a voltage difference between the power voltage ofboth the device and the host. When this voltage difference is in thevicinity of the threshold voltage of a transistor included in thetransfer gate, a leakage current might flow from the differential signalline D+ to the differential signal line D− even if the transfer gate isin an open state. Due to this leakage current and a resistor pullingdown the differential signal line D−, the potential of the differentialsignal line D− may exceed the above-described threshold value. Then,both the potentials of the differential signal lines D+ and D− exceedthe threshold value, and the host cannot recognize the mounting of adevice. Therefore, a semiconductor device and a communication interfacecircuit, for preventing the recognition failure in the mutualrecognition between a host and a device compliant with USBSpecifications are desired.

Note that, the overview of the mutual recognition between a host and adevice in USB Battery Charging Specification 1.2 and the details of aproblem in this case will be described later. Moreover, other problemsand new features will become clear from the description of thisspecification and the accompanying drawings.

According to an embodiment, a semiconductor device includes: aninterterminal opening/closing section having a plurality of firstconductivity type MOS transistors coupled in series; and a currentbypass section that reduces a current flowing into a connection nodeincluded in the interterminal opening/closing section. The semiconductordevice reduces a current flowing into the connection node when theinterterminal opening/closing section is in an open state.

According to another embodiment, a communication interface circuit hasthe above-described semiconductor device arranged between terminals forreceiving a differential signal.

According to an embodiment, a semiconductor device and a communicationinterface circuit, which prevent a recognition failure in the mutualrecognition between a host and a device compliant with USBspecifications, can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view for illustrating the overview of an embodiment;

FIG. 2 is a view showing an example of a USB physical layer in a hostand a device;

FIG. 3 is a view showing an example of the circuit configuration of atransfer gate 20 shown in FIG. 2;

FIG. 4 is a view showing an example of the state of each terminal of ahost 1 and a device 2 in the mutual recognition at the time of a CDP;

FIG. 5 is a view showing an example of the state of each terminal of thehost 1 and the device 2 in the mutual recognition at the time of a DCP;

FIG. 6 is an enlarged view of the waveforms when the host 1 successfullyrecognizes the coupling of the device 2;

FIG. 7 shows an example of the waveforms when the host 1 recognizes thecoupling of the device 2;

FIG. 8 is a view showing an example of the circuit configuration of atransfer gate 21 according to a first embodiment;

FIG. 9 is a view for summarizing the states of a control signal DCP_Eand a transfer gate 21;

FIG. 10 is a view showing an example of the circuit configuration of atransfer gate 20 a;

FIG. 11 is a view showing an example of the circuit configuration of atransfer gate 22 according to a second embodiment; and

FIG. 12 is a view showing an example of the circuit configuration of atransfer gate 23 according to a third embodiment.

DETAILED DESCRIPTION

First, the overview of an embodiment will be described using FIG. 1.Note that, drawing reference numerals given in this overview areattached to the respective components for convenience as an example forhelping understanding of the overview. The description of this overviewis not intended to limit the present invention in any way.

As described above, in a host and a device compliant with USB BatteryCharging Specification 1.2, if there exists a voltage difference betweenthe power source voltages of both the host and the device, then despitethe fact that the device has been mounted on the host, this state mightnot be able to be recognized. Therefore, there is desired asemiconductor device that prevents the recognition failure in the mutualrecognition between a host and a device compliant with the USBspecification.

Therefore, a semiconductor device 100 shown in FIG. 1 is provided as anexample. The semiconductor device 100 shown in FIG. 1 includes: aninterterminal opening/closing section 101 having the first conductivitytype MOS transistors, the respective sources or drains of which arecascaded, in which the source or drain of a first-stage firstconductivity type MOS transistor among the cascaded first conductivitytype MOS transistors is used as a first terminal, in which the source ordrain of a last-stage first conductivity type MOS transistor among thecascaded first conductivity type MOS transistors is used as a secondterminal, and in which the respective gates of the cascaded firstconductivity type MOS transistors receive a control signal forcontrolling the opening or short-circuiting between the first and secondterminals; and a current bypass section 102 that reduces a currentflowing into either one connection node coupling the respective sourcesor drains of the cascaded first conductivity type MOS transistors.

The semiconductor device 100 is used as a transfer gate arranged betweenthe differential signal lines D+ and D− of a USB interface circuit.Moreover, the semiconductor device 100 can switch between the openingand short-circuiting of the interterminal opening/closing section 101 byreceiving a control signal. In contrast, in a CDP of USB BatteryCharging Specification 1.2, the differential signal lines D+ and D− needto be opened. Therefore, at the time of a CDP operation, the firstconductivity type MOS transistors included in the interterminalopening/closing section 101 are set to an off-state. In this case, whenthere is generated a voltage difference in the operating voltage betweena host and a device, a leakage current may be generated in the firstconductivity type MOS transistor as described above. However, even insuch a case, by the operation of the current bypass section 102, thecurrent flowing into a node that mutually couples the first conductivitytype MOS transistors decreases. Then, a current flowing out to thedifferential signal line, to which a power source voltage is notapplied, can be reduced. As a result, an increase in the potential ofthe differential signal line, to which a power source voltage is notapplied, can be suppressed, and a failure in recognizing a device can beprevented.

Furthermore, the following aspects are possible.

[Aspect 1]

A semiconductor device preferably includes: an interterminalopening/closing section having a plurality of first conductivity typeMOS transistors, the respective sources or drains of which are cascaded,in which the source or drain of a first-stage first conductivity typeMOS transistor among the cascaded first conductivity type MOStransistors is used as a first terminal, the source or drain of alast-stage first conductivity type MOS transistor among the cascadedfirst conductivity type MOS transistors is used as a second terminal,and the respective gates of the cascaded first conductivity type MOStransistors receive a control signal for controlling the opening orshort-circuiting between the first and second terminals; and a currentbypass section that reduces a current flowing into either one connectionnode coupling the respective sources or drains of the cascaded firstconductivity type MOS transistors.

[Aspect 2]

The current bypass section preferably feeds a current, which flows intothe connection node, to either a power supply line or a ground line.

[Aspect 3]

Preferably, the current bypass section includes a first conductivitytype MOS transistor, the gate of which receives a signal obtained byinverting the logic of the control signal, or a second conductive MOStransistor, the gate of which receives the control signal.

[Aspect 4]

The semiconductor device preferably includes a first resistor, one endof which is coupled to the source or the drain of the first-stage firstconductivity type MOS transistor and other end of which is used as thefirst terminal, and a second resistor, one end of which is coupled tothe source or the drain of the last-stage first conductivity type MOStransistor and other end of which is used as the second terminal.

[Aspect 5]

The semiconductor device preferably includes a second conductive MOStransistor, the source or drain of which is coupled to the source ordrain of the first-stage first conductivity type MOS transistor andother source or drain of which is coupled to the source or drain of thelast-stage first conductivity type MOS transistor and the gate of whichreceives a signal obtained by inverting the logic of the control signal.

[Aspect 6]

Preferably, the backgates of the first conductivity type MOS transistorsincluded in the interterminal opening/closing section and the backgateof a first conductivity type MOS transistor included in the currentbypass section are mutually coupled.

[Aspect 7]

Preferably, a semiconductor device includes: a first P-channel type MOStransistor, the source or drain of which is used as a first terminal; asecond P-channel type MOS transistor, the source or drain of which iscoupled to the source or drain different from the first terminal andother source or drain of which is coupled is used as a second terminal;and a third P-channel type MOS transistor, the drain of which is coupledto a connection node between the first and second P-channel type MOStransistors and the source of which receives a power source voltage.Preferably, the backgates of the first to third P-channel type MOStransistors are coupled to the power source voltage, and the gates ofthe first and second P-channel type MOS transistors receive a controlsignal for controlling the opening or short-circuiting between the firstand second terminals, and the gate of the third P-channel type MOStransistor receives a signal obtained by inverting the logic of thecontrol signal.

[Aspect 8]

Preferably, a communication interface circuit includes theabove-described semiconductor device, couples the first terminal to aterminal for receiving one of differential signals, and couples thesecond terminal to a terminal for receiving the other differentialsignal.

[Aspect 9]

Preferably, the communication interface circuit complies with USB(Universal Serial Bus) Specifications and transmits/receives data.

Next, an overview of the mutual recognition between a host and a devicein USB Battery Charging Specification 1.2 and the problem in this casewill be described.

As described above, a new additional specification has been formulatedwith respect to USB 2.0 Specification. This additional specificationmainly specifies the battery charging specification on the device sideand describes a method of acquiring an electric power from a USB port onthe host side. USB Battery Charging Specification 1.2 defines threetypes of ports.

A first port is defined as an SDP (Standard Downstream Port). The SDP isthe same port as that defined by USB 2.0 Specification. The upper limitof the power supply capability in the SDP is 5 V/500 mA.

A second port is defined as a CDP. The CDP is the port newly defined inUSB Battery Charging Specification 1.2. The upper limit of the powersupply capability in the CDP is 5 V/1.5 A. In the CDP, datacommunication between a host and a device is possible along with thebattery charging of a device.

A third port is defined as a DCP. The DCP is also the port newly definedin USB Battery Charging Specification 1.2. The upper limit of the powersupply capability in the DCP is also 5 V/1.5 A. However, different fromthe CDP, the data communication between a host and a device cannot beperformed. The DCP does not use the data communication, and is preparedto realize an AC adapter or the like, specific to the battery chargingof a device.

Here, in USB Battery Charging Specification 1.2, there is specified aspecification for determining, by the device side, at which port of anSDP, a CDP and a DCP, a host is operating. This is because if the deviceside cannot determine whether or not a host complies with USB BatteryCharging Specification 1.2, it cannot determine whether or not a highcurrent (1.5 A) can be drawn. Furthermore, if the device side cannotdetermine at which port of a CDP or a DCP, a host operates, it alsocannot determine whether or not emulation (exchange of the configurationinformation of a USB device) is needed.

Note that, which of the three types of ports is to be used is determinedby the host side. For example, if a host compliant with USB BatteryCharging Specification 1.2 is a personal computer, an interface, withwhich a user can determine the setting of each port in advance, isprepared, and in accordance with this setting either one of the threetypes of ports is determined.

Hereinafter, the method of distinguishing between ports in USB BatteryCharging Specification 1.2 is outlined.

As described above, in USB Battery Charging Specification 1.2, in orderto distinguish between a CDP and a DCP, the opening and short-circuitingbetween the differential signal line D+ and D− need to be achieved onthe host side. Therefore, the present inventors have examined thecircuit configuration for implementing this specification.

FIG. 2 is a view showing an example of a USB physical layer in a hostand a device.

A host 1 and a device 2 compliant with USB Battery ChargingSpecification 1.2 are included in the physical layer shown FIG. 2.

The host 1 includes a differential driver 10, a transfer gate 20, adifferential receiver 30, a level shifter 40, an ESD (ElectroStaticDischarge) protection circuit 50, single-ended receivers SEBUF01 andSEBUF02, a comparator CMP01, resistors R01-R04, and N-channel type MOStransistors N01 and N02.

The differential driver 10 converts a single-ended signal generated inan internal circuit (not shown) into a differential signal, and outputsthe same to the differential signal lines D+ and D−. The differentialsignal line D+ is coupled to an input/output terminal H_DP. Similarly,the differential signal line D− is coupled to an input/output terminalH_DM.

The transfer gate 20 is coupled to the differential signal lines D+ andD−, respectively. Note that the following description will be given bydefining a connection node between the differential signal line D+ andthe transfer gate as a node S01 and a connection node between thedifferential signal line D− and the transfer gate 20 as a node S02,respectively. The transfer gate 20 receives a control signal DCP_E. Thetransfer gate 20 controls the opening and short-circuiting between thedifferential signal lines D+ and D− in response to the control signalDCP_E.

FIG. 3 is a view showing an example of the circuit configuration of thetransfer gate 20 shown in FIG. 3. As shown in FIG. 3, the transfer gate20 is constituted by a P-channel type MOS transistor P01. The source ordrain of the P-channel type MOS transistor P01 is coupled to the nodeS01 or S02, and the P-channel type MOS transistor P01 receives thecontrol signal DCP_E at the gate thereof. Furthermore, the backgate ofthe P-channel type MOS transistor P01 is coupled to a power sourcevoltage VDD1 of the host 1.

The differential signal line D+ and the differential signal line D− aregrounded via the resistors R01 and R02 and the N-channel type MOStransistors N01 and N02 (see FIG. 2). The N-channel type MOS transistorsN01 and N02 receive disconnection indication signals RS01 and RS02,which an internal circuit outputs, at their gates, respectively. Theresistor disconnection indication signals RS01 and RS02 are used indisabling the resistors R01 and R02 during a test mode or the like.

The differential receiver 30 receives a differential signal, which thedevice 2 transmits, via the differential signal lines D+ and D− andconverts the same into a single-ended signal and subsequently outputsthe resulting signal to an internal circuit.

The level shifter 40 is coupled to the differential signal lines D+ andD− via resistors R03 and R04, and converts the voltage of a signalpropagating through the differential signal lines D+ and D−. Moreover,by installing the ESD protection circuit 50, the internal circuit andthe like are protected from an ESD discharge entering from theinput/output terminals H_DP and H_DM.

The single-ended receiver SEBUF01 has set therein a voltage SE_TH fordetermining whether or not the voltage of the differential signal lineD+ is higher than a predetermined threshold value. The single-endedreceiver SEBUF01 outputs an H-level when the voltage of the differentialsignal line D+ is higher than the voltage SE_TH. Similarly, thesingle-ended receiver SEBUF02 outputs an H-level when the voltage of thedifferential signal line D− is higher than the voltage SE_TH. A signalthe single-ended receiver SEBUF01 outputs is referred to as a SEPsignal, and a signal the single-ended receiver SEBUF02 outputs isreferred to as a SEM signal. The comparator CMP01 receives the voltageof the differential signal line D+ at the non-inverting input terminalthereof, and receives the voltage DP_TH at the inverting input terminalthereof. The comparator CMP01 outputs an H-level when the voltage of thedifferential signal line D+ is higher than the voltage DP_TH. Note that,the voltage DP_TH and the voltage SE_TH will be described later.

The device 2 transmits/receives the differential signal to/from the host1 via the input/output terminals D_DP and D_DM. Moreover, thedifferential signal line D+ of the device 2 is pulled up to a powersource voltage VDD2 via a resistor R05. Note that, in FIG. 2, disclosedis an example in which the differential signal line D+ of the device 2is pulled up, but the differential signal line D− may be pulled up. Thatis, either the differential signal line D+ or D− of the device 2 may bepulled up.

The mutual recognition between the host 1 and the device 2 starts byelectrical coupling the input/output terminals H_DP and H_DM of the host1 to the input/output terminals D_DP and D_DM of the device 2.

Next, the mutual recognition when the host 1 operates as a CDP will bedescribed.

FIG. 4 is a view showing an example of the state of each terminal of thehost 1 and the device 2 in the mutual recognition at the time of a CDP.

In response to the fact that the device 2 is mounted on the host 1, thevoltage of a VBUS terminal of the device 2 rises to a voltage V01 (e.g.,5.0 V) (at a time t01). Furthermore, because the differential signalline D+ of the device 2 is pulled up to the power source voltage VDD2,the potential of the differential signal line. D+ of the host 1 is alsoset to the power source voltage VDD2 (at a time t02).

When the potential of the input/output terminal H_DP is pulled up to thepower source voltage VDD2, the single-ended receiver SEBUF01 included inthe host 1 sets the SEP signal to an H-level and outputs the same. Thatis, the voltage SE_TH is a threshold voltage for detecting the fact thatthe potential of the input/output terminal H_DP has been pulled up tothe power source voltage VDD2. Here, the potential of the input/outputterminal H_DM maintains the ground voltage. Accordingly, the SEM signalwhich the single-ended receiver SEBUF02 outputs is at an L-level. Whenthe host 1 detects that the SEP signal is at an H-level and the SEMsignal is at an L-level, the host 1 recognizes that the device 2 hasbeen coupled. Otherwise, when the differential signal line D− of thedevice 2 is pulled up, once detecting that the SEP signal is at anL-level and the SEM signal is at an H-level, the host 1 recognizes thatthe device 2 has been coupled. Note that the following description isbased on the premise that the differential signal line D+ of the device2 is pulled up.

Subsequently, the device 2 sets the input/output terminal D_DP to thevoltage V02 (at a time t03). The device 2 notifies the host 1 of thefact that device 2 itself is a device compliant with USB BatteryCharging Specification 1.2 by setting the input/output terminal D_DP tothe voltage V02. Note that, in USB Battery Charging Specification 1.2,the voltage V02 is specified to be in the range from 0.5 V to 0.7 V.

When the potential of the input/output terminal H_DP is set to thevoltage V02, the comparator CMP01 included in the host 1 outputs anH-level. That is, the voltage DP_TH is assumed to be set to a voltage (avoltage in consideration of a margin) slightly lower than the voltageV02.

An internal circuit included in the host 1 recognizes that a devicecompliant with USB Battery Charging Specification 1.2 has been coupled,by the fact that the output of the comparator CMP01 becomes an H-level.Subsequently, the host 1 sets the voltage of the input/output terminalH_DM to the voltage V02 (at a time t04). Then, the host 1 sets thisvoltage to the ground voltage after a predetermined time (at a timet05).

The host 1 notifies the device 2 of the fact that the host 1 itself is ahost compliant with USB Battery Charging Specification 1.2, by settingthe input/output terminal H_DM to the voltage V02.

The device 2 sets the input/output terminal D_DM to the voltage V02after detecting the fact that the host 1 has set the input/outputterminal H_DM to the voltage V02 (time t06). Subsequently, the device 2confirms the potential of the input/output terminal D_DP (time t07). Atthat time, while the host 1 is operating as a CDP, the transfer gate 20is being set to an open state (the differential signal lines D+ and D−are opened) (the control signal DCP_E is being set to an H-level). Then,the potentials of the input/output terminals H_DM and D_DM and thepotential of the input/output terminal D_DP (differential signal lineD+) never agree with each other. Accordingly, in confirming thepotential of the input/output terminal D_DP at a time t07, if thispotential is equal to the ground voltage, the device 2 can recognizethat the host 1 is operating as a CDP.

FIG. 5 is a view showing an example of the state of each terminal of thehost 1 and the device 2 in the mutual recognition at the time of a DCP.When the host 1 operates as a DCP, the control signal DCP_E is set to anL-level. Then, because the transfer gate 20 is in a close state (thedifferential signal lines D+ and D− are short-circuited), the potentialsof the input/output terminals H_DM and D_DM and the potential of theinput/output terminal D_DP (differential signal line D+) agree with eachother. Accordingly, in confirming the potential of the input/outputterminal D_DP at a time t16, if this potential is equal to the voltageV02, the device 2 can recognize that the host 1 is operating as a DCP.Note that, when the host 1 operates as a DCP, the SEP signal and the SEMsignal are not monitored. That is, the operation of detecting the device2 is not performed.

The above is the overview of the mutual recognition in a host and adevice compliant with USB Battery Charging Specification 1.2.

FIG. 6 is an enlarged view of the waveforms when the host 1 successfullyrecognizes the coupling of the device 2. As described above, the host 1recognizes that the device 2 has been coupled, by the SEP signal beingset to an H-level and the SEM signal being set to an L-level. That is,when the port of the host 1 is a CDP, the SEP signal is set to anH-level and the SEM signal is set to an L-level, and thus the host 1 canrecognize the mounting of the device 2.

However, when the host 1 complies with USB Battery ChargingSpecification 1.2, a situation may be contemplated in which the host 1cannot recognize the device 2. That is, when the differential signallines D+ and D− are opened, a situation in which the host 1 cannotrecognize the device 2 may be contemplated.

Here, for the power source voltages of the host 1 and the device 2, theupper limit and the lower limit thereof are specified in USB 2.0Specification. Accordingly, as long as the power source voltages of thehost 1 and the device 2 are within this range, they do not violate thespecification. Then, it is assumed that the power source voltage VDD1 ofthe host 1 is equal to the lower limit and the power source voltage VDD2of the device 2 is equal to the upper limit. Moreover, when the host 1recognizes the device 2 (at the time t02 in FIG. 4 and at a time t12 inFIG. 5), the transfer gate 20 is in an open state.

Since the transfer gate 20 is in an open state, essentially a currentdoes not flow from the differential signal line D+ toward thedifferential signal line D− via the transfer gate 20. However, sincethere is caused a voltage difference between the power source voltageVDD1 of the host 1 and the power source voltage VDD2 of the device 2, aleakage current flows into the P-channel type MOS transistor P01included in the transfer gate 20. That is, a current flows from the nodeS01 toward the node S02.

More specifically, if the power source voltage VDD1 of the host 1=3.0 Vand the power source voltage VDD2 of the device 2=3.6 V, the voltagedifference is 0.6 V. Accordingly, depending on the threshold voltage ofthe P-channel type MOS transistor P01, the P-channel type MOS transistorP01 cannot be set to a complete off-state. Therefore, a leakage currentis generated in the P-channel type MOS transistor P01.

Moreover, the differential signal line D− is pulled down via theresistor R02, and thus a leakage current flowing in via the P-channeltype MOS transistor P01 flows through the resistor R02. As a result, thepotential of the node S02 rises. When the potential (the input voltageof the single-ended receiver SEBUF02) of the node S02 exceeds thevoltage SE_TH, the single-ended receiver SEBUF02 outputs the SEM signalat an H-level.

FIG. 7 shows an example of the waveforms when the host 1 recognizes thecoupling of the device 2. As shown in FIG. 7, when the input voltage ofthe single-ended receiver SEBUF02 exceeds the voltage SE_TH, the SEMsignal is set to an H-level (at a time t32). As described above, thehost 1 can detect the coupling of the device 2 when the SEP signal isbeing set to an H-level and the SEM signal is being set to an L-level,and thus, with the waveforms as shown in FIG. 7, the host 1 cannotsuccessfully recognize the coupling of the device 2. That is, a failurein recognizing the device 2 occurs.

Hereinafter, specific embodiments will be described in more detail withreference to the accompanying drawings.

First Embodiment

A first embodiment will be described in more detail with reference to adrawing.

The difference between a host 3 according to the embodiment and the host1 already described is in that the transfer gate 20 shown in FIG. 2 isreplaced with a transfer gate 21. Therefore, the description of the host3 corresponding to the description of FIG. 2 is omitted.

FIG. 8 is a view showing an example of the circuit configuration of thetransfer gate 21 according to the first embodiment. The transfer gate 21includes P-channel type MOS transistors P02-P04 and an inverter circuitINV01.

The source or drain of the P-channel type MOS transistor P02 is coupledto the node S02, and other source or drain is coupled to the source ordrain of the P-channel type MOS transistor P03. Furthermore, the sourceor drain of the P-channel type MOS transistor P03 is coupled to the nodeS01. The gates of the P-channel type MOS transistors P02 and the P03receive the control signal DCP_E. Note that, with the connection nodebetween the P-channel type MOS transistors P02 and P03 being denoted asa node S03, the following descriptions is given. The P-channel type MOStransistors P02 and P03 correspond to the interterminal opening/closingsection 101 described above.

The source of the P-channel type MOS transistor P04 is coupled to thepower source voltage VDD1, the drain thereof is coupled to the node S03,and the gate thereof receives the control signal DCP_E inverted by theinverter circuit INV01. The P-channel type MOS transistor P04corresponds to the current bypass section 102 described above.

The backgates of the P-channel type MOS transistors P02 to P04 aremutually coupled to the power source voltage VDD1. Note that thebackgates of the P-channel type MOS transistors P02-P04 are not limitedto being mutually coupled. These backgates may be individually coupledto the power source voltage VDD1.

The transfer gate 21 when the control signal DCP_E is at an L-level,short-circuits the nodes S01 and S02. That is, the interterminalopening/closing section constituted by the P-channel type MOStransistors P02 and P03 short-circuits the differential signal lines D+and D−. At that time, the P-channel type MOS transistor P04 is in anoff-state, and thus a current does not flow from the node S03 toward thepower source voltage VDD1.

In contrast, the transfer gate 21, when the control signal DCP_E is atan H-level, opens the nodes S01 and S02. In this case, the P-channeltype MOS transistor P04 is in an on-state, so a current path from thenode S03 toward the power source voltage VDD can be formed. FIG. 9 is aview for summarizing the states of the control signal DCP_E and thetransfer gate 21.

Next, the operation of the host 3 including the transfer gate 21 will bedescribed.

At that time, it is assumed that the host 3 operates as a CDP. The host3, in order to operate as a CDP, always sets the control signal DCP_E toan H-level and sets the transfer gate 21 to an open state. Moreover,since the control signal DCP_E is at an H-level, the P-channel type MOStransistor P04 is in an on-state. When the device 2 is coupled to thehost 3, the potential of the input/output terminal H_DP of the host 3increases, and at a time point when it exceeds the voltage SE_TH, theSEP signal becomes an H-level. In this case, if a voltage equal to orgreater than the power source voltage of the host 3 is applied to theinput/output terminal H_DP, a leakage current flows into the node S03via the P-channel type MOS transistor P03 included in the transfer gate21.

However, since the P-channel type MOS transistor P04 arranged betweenthe node S03 and the power source voltage VDD is in an on-state, most ofthe current flowing into the node S03 flows to the power supply line viathe P-channel type MOS transistor P04. As a result, the current flowinginto the input/output terminal H_DM via the P-channel type MOStransistor P02 can be suppressed.

The current flowing into the input/output terminal H_DM decreases, andthus an increase in the potential of the input/output terminal H_DM(differential signal line D−) can be suppressed. Therefore, the inputvoltage to the single-ended receiver SEBUF02 does not exceed the voltageSE_TH and the SEM signal is maintained at an L-level. That is, in thehost 3 according to the embodiment, a failure in recognizing the device2 does not occur.

Here, as a measure for preventing a failure in recognizing the device 2,the following measures can be contemplated.

A first measure is to increase the threshold voltage of the P-channeltype MOS transistor P01 included in the transfer gate 20. The currentvalue of a current flowing into the input/output terminal H_DM via theP-channel type MOS transistor P01 depends on a difference between thepower source voltage VDD1 of the host 1 and the power source voltageVDD2 of the device 2, and depends on the threshold voltage of theP-channel type MOS transistor P01. Therefore, the generation of aleakage current can be suppressed by increasing the threshold voltage ofthe P-channel type MOS transistor P01.

However, in such a countermeasure, a modification such as formation ofthe gate oxide film of the P-channel type MOS transistor P01 so as to bethicker than the gate oxide film of other P-channel type MOS transistorsincluded in the host 1, is needed. That is, a P-channel type MOStransistor with a high threshold voltage needs to be specially prepared,which poses a problem in terms of effective use of the substrate area.

In contrast, for the P-channel type MOS transistors P02-P04 used for thetransfer gate 21 according to the embodiment, the threshold voltagethereof does not need to be increased as compared with other P-channeltype MOS transistors, and thus such a problem does not occur.

A second measure is to employ a configuration in which a plurality ofP-channel type MOS transistors is cascaded.

FIG. 10 is a view showing an example of the circuit configuration of atransfer gate 20 a. As shown in FIG. 10, by cascading the P-channel typeMOS transistors, a current flowing into the input/output terminal H_DMcan be reduced. However, in such a countermeasure, a number of P-channeltype MOS transistors are needed, and problems, such as an increase ofthe substrate area and an increase of the cost, occur. In contrast, thenumber of P-channel type MOS transistors used for the transfer gate 21according to the embodiment is limited, and the substrate area does notincrease.

In the present embodiment, a case where a host and a device are coupledto each other, and the prevention of the recognition failure that thehost cannot recognize the device have been described. However, even whena USB hub and a device are coupled to each other, needless to say that afailure in recognizing the device in the USB hub can be prevented.Accordingly, the transfer gate 21 according to the embodiment issuitably applied to a host controller or a HUB controller compliant withUSB 2.0 Specification (including USB Specification Revision 1.1).Moreover, at present, USB Specifications have been determined up toRevision 3.0, but in USB Specification Revision 3.0, the batterycharging specification at high electric power of such as 1.5 A has notbeen specified yet. For this reason, even in a host controller or thelike compliant with USB 3.0, fast battery charging in accordance withUSB Battery Charging Specification 1.2 is planned. Accordingly, even ifthe transfer gate 21 according to the embodiment is used for a hostcontroller or a HUB controller compliant with USB 3.0, the same effectcan be expected.

Furthermore, all the transistors included in the transfer gate 21 areP-channel type MOS transistors, but are not limiting. For example, inplace of the P-channel type MOS transistor P04, an N-channel type MOStransistor may be arranged. This is because even with an N-channel typeMOS transistor, a current can be fed from the node S03 to the groundline. However, the use of an N-channel type MOS transistor results in ahigher current flowing into the ground line, and there is a concern thatthe power source voltage VDD1 drops due to the influence of theon-resistance of the N-channel type MOS transistor. Therefore, asdescribed in the embodiment, all the transistors included in thetransfer gate 21 are preferably unified by either P-channel type MOStransistors or N-channel type MOS transistors. This is because ifunified by either of them, the current value of a current flowing out ofthe node S03 is limited (because the current value of a current flowingfrom the node S03 depends on a difference between the power sourcevoltage VDD1 and the power source voltage VDD2).

Furthermore, a measure for reducing the current flowing into the nodeS03 is not limited to feeding a current into the power supply line orthe ground line by turning on/off a transistor. For example, the currentflowing into the node S03 can be reduced by coupling one end of acapacitive element to the node S03 and thereby absorbing the currentflowing into the node S03. In this case, the charge stored in thecapacitive element may be discharged during an operation mode that doesnot affect the operations of a host and a device.

As described above, in the mutual recognition between a host and adevice compliant with USB Battery Charging Specification 1.2, a problemoccurs such as that the host cannot successfully recognize the devicedue to an increase in the potential of the input/output terminal H_DM(differential signal line D−). Then, the transfer gate 21 constituted bythe P-channel type MOS transistors P02-P04 is used. The transfer gate 21sets the P-channel type MOS transistor P04 to an on-state when the nodeS01 and S02 are opened. By setting the P-channel type MOS transistor P04to an on-state, even when there is a voltage difference between thepower source voltage VDD1 of a host and the power source voltage VDD2 ofa device, the generated leakage current is absorbed by the power supplyvia the P-channel type MOS transistor P04. As a result, the currentflowing into the input/output terminal H_DM decreases, and the voltagethe single-ended receiver SEBUF02 receives does not rise. That is, thesingle-ended receiver SEBUF02 does not output an H-level as the SEMsignal, and thus a failure in recognizing the device can be prevented.

Second Embodiment

Subsequently, a second embodiment will be described in detail withreference to the drawing.

The transfer gate 21 according to the first embodiment is coupled to theinput/output terminals H_DP and to the H_DM without via a resistor.Therefore, the transfer gate 21 may be susceptible to ESD discharge.Accordingly, an increase of the resistance of the transfer gate 21against ESD discharge is desired.

FIG. 11 is a view showing an example of the circuit configuration of atransfer gate 22 according to the second embodiment. In FIG. 11, thesame symbol is attached to the same component as that of FIG. 8, and thedescription thereof is omitted.

The difference between the transfer gate 21 and the transfer gate 22 isin that a resistor R06 is coupled between the P-channel type MOStransistor P03 and the nodes S01 and a resistor R07 is coupled betweenthe P-channel type MOS transistor P02 and the nodes S02, respectively.Note that the resistance values of the resistors R06 and R07 aredetermined within a range in which the resistance value from the nodeS01 to the node S02 (the resistance values of the resistors R06 and R07and the on-resistances of the P-channel type MOS transistors P02 andP03) does not depart from a specification determined by USB BatteryCharging Specification 1.2.

As described above, in order to overcome the susceptibility of thetransfer gate 21 against ESD discharge, the resistors R06 and R07 arecoupled. As a result, the resistance of the transfer gate 22 and theresistance of a host including the transfer gate 22 against ESDdischarge are improved.

Third Embodiment

Subsequently, a third embodiment will be described in detail withreference to the drawing.

As described above, in the mutual recognition between a host and adevice, when the host operates as a DCP, the differential signal linesD+ and D− are short-circuited. Because the differential signal lines D+and D− are short-circuited, the device can recognize that the hostoperates as a DCP. In this case, in the transfer gate, the voltage V02that is a low voltage needs to be passed therethrough. Note that, asdescribed above, in USB Battery Charging Specification 1.2, the voltageV02 is specified as 0.5 V to 0.7 V.

Therefore, in the transfer gate 21 or 22 constituted only by P-channeltype MOS transistors, it is difficult to cause the voltage V02 to passtherethrough. This is because in order for a P-channel type MOStransistor to be turned on, the gate voltage needs to exceed thethreshold voltage with reference to the source voltage.

FIG. 12 is a view showing an example of the circuit configuration of atransfer gate 23 according to a third embodiment. In FIG. 12, the samesymbol is attached to the same component as that of FIG. 11, and thedescription thereof is omitted.

The difference between the transfer gate 23 and the transfer gate 22 isin that an N-channel type MOS transistor N03 is added. The source ordrain of the N-channel type MOS transistor N03 is coupled to theresistor R06, and other source or drain is coupled to the resistor R07.Furthermore, the gate of the N-channel type MOS transistor N03 receivesthe output of the inverter circuit INV01, and the backgate thereof isgrounded.

In this manner, adding the N-channel type MOS transistor N03 to thetransfer gate 22 facilitates a low voltages signal to pass through thetransfer gate 22. This is because the passing through of a low voltagesignal is easy because an N-channel type MOS transistor is turned onwhen the gate voltage exceeds the threshold voltage with reference tothe source voltage.

Note that, in the transfer gate 23 according to the embodiment, anN-channel type MOS transistor is added to the transfer gate 22 accordingto the second embodiment. However, an N-channel type MOS transistor maybe added to the transfer gate 21 according to the first embodiment. Alsoin such a case, the effect of easily causing a low voltages signal topass through the transfer gate 21 can be expected.

Here, in the first to third embodiments, the description is givenassuming that the transistor included in the transfer gate is aP-channel type MOS transistor. However, even if the P-channel type MOStransistor is interchanged with an N-channel type MOS transistor, thetransfer gate can accordingly work if the couplings of the power supplyand the like are arbitrarily modified. That is, the P-channel type MOStransistor can be regarded as the first conductivity type MOStransistor, and the N-channel type MOS transistor can be regarded as thesecond conductive MOS transistor. Furthermore, the use of the transfergates 21-23 for a communication interface circuit compliant with USBSpecifications has been described, but not limited to the USBSpecifications, and needless to say that the transfer gates 21-23 can beapplied to telecommunication specifications, in which the mutualrecognition between a host and a device is carried out by the sameprocedure.

Note that, each disclosure of the Patent Documents and the like citedabove is hereby incorporated by reference in its entirety. Within thescope of all disclosures (including the scope of the claims) of thepresent invention, and furthermore, on the basis of their basictechnical ideas, modification and adjustment of the embodiments and/orthe examples are possible. Moreover, within the scope of the claims ofthe present invention, a variety of combinations and/or selections ofthe various disclosed components (including each component of eachclaim, each component of each embodiment and/or an example, eachcomponent of each drawing, and the like) are possible. That is, it isneedless to say that the present invention includes various kinds ofvariants and corrections, which those skilled in the art may make inaccordance with all the disclosures and technical ideas including theclaims.

1-9. (canceled)
 10. A semiconductor device, comprising: an interterminalopening/closing section having a plurality of first conductivity typeMOS transistors, the respective sources or drains of which are cascaded,wherein a source or drain of a first-stage first conductivity type MOStransistor among the cascaded first conductivity type MOS transistors isused as a first terminal, wherein a source or drain of a last-stagefirst conductivity type MOS transistor among the cascaded firstconductivity type MOS transistors is used as a second terminal, whereinthe respective gates of the cascaded first conductivity type MOStransistors receive a control signal for controlling an opening orshort-circuiting between the first and second terminals, wherein saidfirst and second terminals are coupled to respective first and seconddifferential signal lines each connected to a respective one of a pairof input/output terminals of a host, wherein said semiconductor devicefurther comprises a first single-ended receiver constructed to output afirst signal based on whether or not a voltage present at said firstdifferential signal line exceeds a threshold voltage and a secondsingle-ended receiver constructed to output a second signal based onwhether or not a voltage present at said second differential signal lineexceeds said threshold voltage, and wherein said host is configured todetermine that a device has been coupled to said pair of input/outputterminals of the host based on said first and second signals havingdifferent states.
 11. The semiconductor device according to claim 10,further comprising: a first resistor, one end of which is coupled to thesource or drain of the first-stage first conductivity type MOStransistor and other end of which is used as the first terminal; and asecond resistor, one end of which is coupled to the source or drain ofthe last-stage first conductivity type MOS transistor and other end ofwhich is used as the second terminal.
 12. The semiconductor deviceaccording to claim 11, wherein backgates of the first conductivity typeMOS transistors included in the interterminal opening/closing sectionare mutually coupled.
 13. A semiconductor device comprising: a firstP-channel type MOS transistor, a source or drain of which is used as afirst terminal; and a second P-channel type MOS transistor, a source ordrain of which is coupled to the source or drain different from thefirst terminal and other source or drain of which is used as a secondterminal, wherein gates of the first and second P-channel type MOStransistors receive a control signal for controlling an opening orshort-circuiting between the first and second terminals, wherein saidfirst and second terminals are coupled to respective first and seconddifferential signal lines each connected to a respective one of a pairof input/output terminals of a host, wherein said semiconductor devicefurther comprises a first single-ended receiver constructed to output afirst signal based on whether or not a voltage present at said firstdifferential signal line exceeds a threshold voltage, and a secondsingle-ended receiver constructed to output a second signal based onwhether or not a voltage present at said second differential signal lineexceeds said threshold voltage, and wherein said host is configured todetermine that a device has been coupled to said pair of input/outputterminals of the host based on said first and second signals havingdifferent states.
 14. A communication interface circuit comprising: aninterterminal opening/closing section having a plurality of firstconductivity type MOS transistors, the respective sources or drains ofwhich are cascaded, wherein a source or drain of a first-stage firstconductivity type MOS transistor among the cascaded first conductivitytype MOS transistors is used as a first terminal, wherein a source ordrain of a last-stage first conductivity type MOS transistor among thecascaded first conductivity type MOS transistors is used as a secondterminal, wherein the respective gates of the cascaded firstconductivity type MOS transistors receive a control signal forcontrolling an opening or short-circuiting between the first and secondterminals, wherein the first terminal is coupled to a terminal forreceiving one of a pair of differential signals, wherein the secondterminal is coupled to a terminal for receiving the other of a pair ofdifferential signals, wherein said first and second terminals and saidpair of differential signal lines are connected to a pair ofinput/output terminals of a host, wherein said communication interfacecircuit further comprises a first single-ended receiver constructed tooutput a first signal based on whether or not a voltage present at saidfirst differential signal line exceeds a threshold voltage, and a secondsingle-ended receiver constructed to output a second signal based onwhether or not a voltage present at said second differential signal lineexceeds said threshold voltage, and wherein said host is configured todetermine that a device has been coupled to said pair of input/outputterminals of the host based on said first and second signals havingdifferent states.
 15. The communication interface circuit according toclaim 14, wherein the communication interface circuit complies with USB(Universal Serial Bus) specifications for transmitting/receiving data.16. The semiconductor device according to claim 10, wherein each saidfirst-stage first conductivity type MOS transistor is a firstconductivity type-only MOS transistor.
 17. The communication interfacecircuit according to claim 14, wherein each said first-stage firstconductivity type MOS transistor is a first conductivity type-only MOStransistor.